1. Field of the Invention
The present invention relates to a semiconductor device having, e.g., a transistor and capacitor, and a method of manufacturing the same.
2. Description of the Related Art
With the recent advancing micropatterning of DRAMs (Dynamic Random Access Memories), a gate length L and gate width W of a cell transistor are decreasing, and this poses the problems of deterioration of the short-channel effect and the reduction of a driving electric current.
Also, as shown in FIG. 21, in a DRAM having a trench capacitor using a BS (Buried Strap), micro-patterning reduces the distance between a BS diffusion layer 125b and cell transistor 134. Therefore, misalignment between a capacitor 117 and gate electrode 128 allows the BS diffusion layer 125b to easily reach the channel region of the cell transistor 134. This deteriorates the short channel effect or causes punch through. Accordingly, very high alignment accuracy is required.
Note that prior art reference information related to the invention of this application is, e.g., “Jpn. Pat. Appln. KOKAI Publication No. 2000-196045”.